A liquid crystal display device in an Advanced Super Dimension Switch (ADS) mode has been widely used due to its advantages such as high aperture ratio and wide view angle.
As shown in FIG. 1 and FIG. 2, an existing array substrate in an ADS mode comprises a base 9, and known structures such as data lines 81, gate lines 82, thin film transistors (each of which comprises an active region 7, a source 71, a drain 72, a gate, and a gate insulating layer 73) are provided on the base 9. The drain 72 of the thin film transistor is connected to the pixel electrode 1, an insulating layer 2 (PVX) is provided above the pixel electrode 1, and a common electrode 3 with slits 39 is provided above the insulating layer 2. It can be seen from above that, the performance of the thin film transistor of its own has a significant effect on a voltage of the pixel electrode (i.e., display effect). Therefore, it is necessary to test the performance of the thin film transistor before the array substrate is shipped. In an existing test method, a test pin 5 is in contact with the pixel electrode 1, and a test signal is inputted to the data line 81 and the gate line 82, so that currents in the thin film transistor under various gate voltages can be tested using the test pin 5.
As shown in FIG. 2, in the above array substrate, the pixel electrode 1 is provided with an insulating layer 2 (and further parts of the common electrode excluding the slits 39) thereabove, therefore, it is impossible for the test pin 5 to come into contact with the pixel electrode 1, and thus thin film transistors in the respective pixel units cannot be tested directly. Therefore, it is necessary to additionally provide test thin film transistors in edge regions other than the display region (which is a region for displaying in the center of the array substrate), wherein the test thin film transistors are manufactured in synchronization with the thin film transistors in the display region, but are not connected to other structures such as the pixel electrode 1 and are specially used to test.
The inventor finds at least following problems existing in the related art:
The edge region and the display region of the array substrate are different in structure, for example, there is no electrode provided in the edge region, and during manufacturing the array substrate, the display region is protected in many procedures, in contrast, no protection measure is taken for the edge region. In summary, the test thin film transistor is subjected to a different process environment from the thin film transistors in the display region, and such a difference will affect the performance of the thin film transistor. Therefore, the performance of the test thin film transistor is not necessarily the same as that of the thin film transistor in the display region, and thus the performance of the thin film transistor in the display region cannot be accurately determined depending on the performance of the test thin film transistor. For example, among the performance test curves shown in FIG. 3, the curve of the test thin film transistor is not coincided with the standard curve, which represents that the performance of the test thin film transistor is unqualified, however, it can not be determined whether or not the performance of the thin film transistor at the display region is also unqualified as the test thin film transistor, therefore, the test result is not accurate and just only used as a reference.